Digital imaging devices are currently implemented in many types of electronic devices. These electronic devices may include digital still cameras, digital video cameras, mobile camera-phones, computer web-cams, and other types of devices. Semiconductor components are commonly used to capture images and digitally process the captured images. These semiconductor components may include charge coupled devices and complementary metal-oxide semiconductors. To capture or acquire images, digital imaging devices often use a sensor array made of an arranged pattern of photodiodes. This type of sensor array is commonly known as a “pixel array.”
One of the problems encountered by conventional digital imaging devices is “flicker.” Artificial lighting that uses an alternating current (AC) source, such as fluorescent lighting, contains a brightness modulation component known as flicker. The frequency of flicker for artificial lighting is twice the frequency of an AC source. For example, a 50 Hz AC power system and a 60 Hz AC power system result in 100 Hz and 120 Hz flicker frequencies, respectively. Flicker arises during image capturing when an electronic device and the frequency of an AC source are not synchronized. As an example, a frame rate commonly used in the electronics industry is 30 Hz. When this frame rate is used, flicker can result from artificial lighting employing a 50 Hz AC power system.
In conventional digital imaging devices, flicker typically causes a periodic variation in the luminance of captured images. This effect is often referred to as “banding.” Banding may be common, for example, in devices that capture an image in a row-by-row fashion, where all pixel elements in a sensor row are exposed simultaneously but the onset of exposure is delayed from row to row. Consequently, the banding effect appears in a captured image as horizontal strips of different luminance. This may reduce the aesthetic quality of the captured image significantly.
The following represents a more detailed discussion of the effects of flicker based on conventional pixel elements in a conventional digital imaging device. Each pixel element typically includes a photodiode and other integrated circuitry. The photodiode generates a current according to the amount of light detected, and a sum charge is stored in an integrated capacitor. The stored charge is then converted into an output voltage, where the output voltage is proportional to the amount of charge stored in the capacitor. After that, an analog-to-digital converter converts the output voltages of the pixel elements into digital values, and the digital values are processed into a digital image. In particular, the output signal of a pixel element may be derived from integrating the photodiode current through the capacitor, as shown in the following equation:V=I*t/c  (1)where V is the output voltage of the pixel element, I is the photodiode current, t is the integrating time or exposure timing, and C is the parasitic capacitance of the pixel element.
The integrating time t of a pixel element may have a wide range of values to enable a pixel array to operate in a wide range of lighting conditions. As shown in FIG. 1A, constant output signals (denoted “Output1” and “Output2”) may be produced when the integrating time t corresponds to one period of the lighting frequency cycle (denoted “Light Variation”). As a result, no effects from flicker occur in this example. In contrast, FIG. 1B illustrates a difference in the output signals when the integrating time t is less than one period of the lighting frequency cycle. This difference in the output signals may cause a captured image to suffer from banding.
Several techniques have been used to try to overcome the effects of flicker. For example, in typical digital imaging devices, a user can manually set the lighting frequency or manually select the best image captured using different frequency settings. In another technique, a digital imaging device can automatically select the lighting frequency by detecting the country on which system configuration data is based. This can be achieved, for example, by integrating a wireless connection (such as a global positioning system) or a wired connection to the AC power system. However, additional circuitry and costs are introduced using this technique.
In yet another technique, a digital imaging device utilizes a digital imager with an integrated flicker detector. The flicker detector monitors the lighting frequency and adjusts the digital imaging device to the appropriate lighting frequency. The flicker detector thereby provides a mechanism for allowing the digital imaging device to adjust to current lighting conditions. As a particular example, the digital imaging device may rely on the amount of light detected and adjust the sensor array to the appropriate exposure timing, thereby reducing or eliminating any effects of flicker on captured images. This technique may overcome the inconvenience of manually setting the lighting frequency by the user, who is usually unaware of the AC power frequency in a specific country. Also, the flicker detector can be manufactured in the same semiconductor fabrication process as the digital imager, thereby reducing costs and any additional circuitry.
FIG. 2 illustrates a conventional gain control circuit 200 in a flicker detector. The gain control circuit 200 includes a photodiode 202, a variable capacitance circuit 204, and a buffer 206. The photodiode 202 is coupled to an input terminal of the buffer 206 via a cascode transistor 208. A reset component 210, such as a transistor switch, is coupled to an integration node 212. The integration node 212 is disposed on an interconnection between a drain terminal of the transistor 208 and the input terminal of the buffer 206.
For a new image acquisition, the reset component 210 is closed to initialize the integration node 212 to a reset voltage (denoted Vrt). This helps to ensure that the gain control circuit 200 has the same starting voltage before the circuit 200 begins an integration. When the reset component 210 is opened, the photodiode 202 generates a current according to the amount of light detected. The transistor 208 collects the discharged photodiode current Iphoto for integration at the integration node 212. The transistor 208 also separates a large parasitic capacitance Cphoto of the photodiode 202 from the integration node 212. The buffer 206 drives an output load and separates an output load capacitance Cload from the integration node 212. By reading the integration node 212 twice (once after reset and once after exposure to light), a voltage difference may be determined, which is directly proportional to the charge stored at the integration capacitor (represented by CIntNode and Cvar). The voltage difference represents an output voltage Vout of the gain control circuit 200, which may be defined by the equation:Vout=(Iphoto*Tint)/(CIntNode+Cvar)  (2)where Tint is the integrating time or exposure timing, and Cvar represents the only variable parameter.
In contrast with equation (1), the time parameter Tint in equation (2) is constant in order to detect a light variation. Applying Nyquist sampling theory, the duration of Tint should be shorter than the flicker period to effectively sample any flicker (as shown in FIG. 1C). For example, in a 50 Hz AC power system, the value of Tint may be fixed at 10 ms.
The maximum gain and Vout amplitude may be obtained in the circuit 200 when (CIntNode+Cvar) is at a minimum level. This may require setting Cvar to zero and minimizing CIntNode. In order to minimize CIntNode, the reset component 210, buffer 206, and transistor 208 coupled to the integration node 212 may be designed to have the lowest possible parasitic capacitance. Also, these elements may be connected as close as possible to each other to minimize wiring capacitance. The minimum gain and Vout amplitude may be obtained when (CIntNode+Cvar) is at a maximum level. This may require setting Cvar to the maximum level. The range of gain of the gain control circuit 200 may therefore be limited by the factor:Range=(CIntNode+Max(Cvar))/CIntNode.  (3)
Referring to FIG. 3A, a conventional variable capacitance circuit 204 includes a plurality of Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) 302-308 with increasing gate sizes. In illustrating the operation of the variable capacitance circuit 204, suppose that when the transistor 302 is turned off, Cvar=CGD11 as shown in FIG. 3B. The integration capacitor is now the gate-drain capacitance of the transistor 302.
Although the conventional variable capacitance circuit 204 provides variable capacitor control for the gain control circuit 200, there are several drawbacks to this circuit 204. For example, the parasitic capacitance is being added into the integration capacitor even though the transistor 302 is turned off. Referring to FIG. 3C, when the transistor 304 is off, CS11+D12 still contributes to the value of Cvar. Another drawback is that the circuit 204 uses gate-source and/or gate-drain capacitances of the transistors 302-308 instead of gate-bulk capacitances. The gate-bulk capacitances have larger parasitic capacitances than gate-source or gate-drain capacitances but are not utilized for Cvar. Hence, Cvar does not fully utilize the parasitic capacitance available in the surface area of the transistors 302-308. Yet another drawback is that noise from VDD and GND terminals may affect the signal-to-noise ratio of the circuit 204, and noise from the VDD terminal may be prominent in devices such as charge-pump devices.
In view of these problems, the conventional gain control circuit 200 has a limited range of gain (because Cvar is the only variable parameter available). Also, a larger amount of surface area in the transistors 302-308 may be required to achieve an effective range increase for the gain control circuit 200, which increases manufacturing costs. In addition, the variable capacitance circuit 204 may be sensitive to supply pollution, thus reducing the signal-to-noise ratio of the overall gain control circuit 200.